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SYSTEM DEVELOPMENT

Fabric Test for Mil/Aero Systems: The Cost-Effective Way

Switched fabrics enable impressive throughputs in VPX and VXS. But the reality of that performance falls short unless each serial link is optimized. SerDes test blades ease the way.

MOHAMED HAFED, PH.D. & JUSTIN MOLL, DFT MICROSYSTEMS & ELMA ELECTRONIC

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VPX and VXS continue to gain acceptance among developers of military and aerospace systems. These VME follow-on architectures employ fabric schemes such as Serial RapidIO and PCI Express to provide impressive system throughput. All that said, exploiting such serial fabric technologies to their maximum potential requires careful system optimization even at the physical level. Excessive signal attenuation, for example, across backplane traces can result in sub-optimal system performance. So instead of achieving the theoretical aggregate bandwidth or system throughput associated with the technology, often a much lower throughput results because of the poor error rate and the constant need to retransmit erroneous packets.

To maximize performance of VPX and VXS mil/aero systems, the behavior of each serial link in each slot in a populated backplane system needs to be optimized. Doing this calls for the use of test blades: dedicated standard plug-in high-speed serial boards. These enable the optimization of serial links from any slot and any system configuration.

Losses associated with variable backplane trace lengths are dependent on fabric topology. To deal with those losses, new serial transmitters can compensate by controlling parameters such as pre-emphasis and current boost. For example, a typical commercial Serial RIO device offers register control for driver strength, supply current and driver pre-emphasis. By selecting different driver settings on the device, backplane trace losses can be compensated. Figure 1 shows an example of two eye diagrams for a single serial link but with different driver pre-emphasis settings.

768 Different Driver Settings

Programmable drivers offer hundreds of settings that the system integrator can control. In fact, the typical example device mentioned above provides 768 different driver settings. With that degree of programmability, the question arises as to how a system integrator can know what driver settings to use for his or her specific system. Moreover, the amount of pre-emphasis or “boosting” is–naturally–slot dependent. The farther a slot is from the source, the more trace loss it is subjected to. In fact, no one driver setting will be applicable to all slots in a backplane. This is illustrated in Figure 2, which depicts eye diagrams obtained from a five-slot VPX chassis. A pre-emphasis setting that enables a link from slot 1 to slot 2 to pass the Serial RapidIO compliance mask is not adequate for a driver connected from slot 1 to slot 5. Clearly, a different driver setting is required for communication with slot 5 than for slot 2. When the appropriate setting is selected for the link connected to slot 5, the resulting eye diagram is as shown in Figure 3.

SerDes Test Blades

As can be seen from the above examples, there is a need for a configuration-specific tuning of transmitter pre-emphasis parameters in a system. This is where SerDes test blades, such as the DV3200 VPX SerDes Test Blade from Elma Electronic–developed in cooperation with partner DFT MicroSystems–come in. A test blade is a tool that is specifically designed to perform driver pre-emphasis tuning in a populated backplane, and it results in unprecedented productivity/efficiency gains over conventional methodologies.

Note that since VPX and VXS share the same Multi-Gig family connector, it is fairly simple to create a test blade module based on VXS. The “intelligence” of the test card is on a small module that can fit on various form factors. Figure 4 shows a schematic illustration and a photograph of a SerDes test blade that is connected to a backplane system. As can be seen, it has several important characteristics. First, it is a single-slot blade that is designed to be compliant to the target specification. For example, for the VPX standard, a test blade has a standard 6U or 3U form factor, and it connects directly to the backplane connectors in the VPX system. Second, the test blade has no external connections to test and measurement equipment. It is fully contained and is capable of performing all the functions necessary for backplane signal optimization. Third, the test blade has a USB connection to a host PC. The PC runs an easy-to-use graphcal user interface that enables access to all the test blade functions. In the next section, the use of test blades for driver pre-emphasis tuning is described.

The driver pre-emphasis tuning process involves installing the “source” blade into the slot for which it is intended. The source blade is the board for which the serial driver parameters are being optimized. Meanwhile, the SerDes test blade is installed at the slot where the “destination” blade is anticipated to be placed. This is the slot at which the serial link for the “source” blade is terminated. For a slot 1 to slot 5 connection, let’s say the source blade is installed in slot 1 and the test blade in slot 5. At this point, the hardware setup is complete, without requiring any external bench-top equipment.

Next come the software steps. The source blade is programmed to generate a test pattern, such as a PRBS7 pattern. Most new serial devices include test patterns such as this example. Subsequently, the SerDes test blade is programmed to lock onto the test pattern and measure signal parameters such as eye diagrams and bit-error-rate. Once this is done, a software loop is started in which the driver pre-emphasis settings are incremented sequentially and eye diagrams are collected for each driver setting. The eye diagrams are analyzed within the test blade software environment to assess compliance to a specified mask (such as Serial RapidIO). The loop terminates as soon as the eye diagram passes compliance.

At this stage, the appropriate driver pre-emphasis setting is recorded for the source blade. This setting represents the optimal setting for the source blade in the specific system configuration. Specifically, if the source blade happens to be installed in a different system, the optimization process needs to be repeated for the new system. Figure 5 shows the eye diagram optimization process graphically using real data from a 5-slot VPX chassis.

True Bit-Error-Rate Optimization

SerDes test blades, such as the DV3200, offer more than just eye diagram plots as shown earlier. In fact, they provide detailed analysis functions for the complete evaluation of serial link transmitters as well as receivers. Most importantly, they offer the opportunity to evaluate bit-error-rate (BER) performance of systems under varying conditions (ambient conditions, software conditions, computing payload and so on). Figure 6 shows various BER contour plots that are captured using a test blade. Contour plots are useful utilities to evaluate the amount of margin in serial links.

SerDes test blades represent a truly compelling productivity enhancement solution for VPX and VXS users in the military and aerospace industry. All that is required to operate a test blade is a PC with the appropriate software loaded, USB cables and one or more test blades. This approach enables system-level optimization to occur simply and with great efficiency.

DFT Microsystems
Montreal, Quebec
Canada.
(514) 878-8271.
[www.dftmicrosystems.ca].

Elma Electronic
Fremont, CA.
(510) 656-3400.
[www.elma.com].

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